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1 fn6666.5 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | intersil (and design) is a trademark owned by intersil corporation or one of its subsidiaries. copyright intersil americas inc. 2008, 2011. all rights reserved all other trademarks mentioned are the property of their respective owners. isl62391, isl62392, isl62391c, isl62392c high-efficiency, triple-output system power supply controller for notebook computers the isl62391, isl62392, isl62391c and isl62392c controller generate supply voltages for battery-powered systems. it includes two pulse-width modulation (pwm) controllers, adjustable from 0.6v to 5.5v, and a linear regulator (ldo3) that generates a fixed 3.3v and can deliver up to 100ma. the isl62391, isl62392, isl62391c and isl62392c include on-board power-up sequencing, a power- good (pgood) output, digital soft-start, and internal soft-stop output discharge that prevents negative voltages on shutdown. the patented r 3 pwm control scheme provides a low jitter system with fast response to load transients. light-load efficiency is improved with period-stretching discontinuous conduction mode (dcm) operation. to eliminate noise in audio frequency applications, an ultrasonic dcm mode is included, which limits the minimum switching frequency to 28khz. the isl62391, isl62391c and isl62392, isl62392c are identical except for how their overvoltage protection is handled. the isl62391 and isl62391c utilize a tri-state overvoltage scheme, whereas the isl62392 and isl62392c employ a soft-crowbar method. the isl62391, isl62392, isl62391c and isl62392c are available in a 28 ld 4x4 tqfn package and operate over the extended temperature range (-40c to +100c). features ? high performance r 3 technology ? fast transient response ? 1% output voltage accuracy ? 2 fully programmable switch-mode power supplies ? programmable switching frequency ? fixed 3.3v ldo output ? internal soft-start and soft-stop output discharge ? wide input voltage range: 5.5v to 25v ? full and ultrasonic pulse-skipping mode ? power-good indicator ? overvoltage, undervoltage and overcurrent protection ? thermal monitor and protection ? pb-free (rohs compliant) applications ? notebook and sub-notebook computers ? pdas and mobile communication devices ? 3-cell and 4-cell li+ battery-powered devices pinout isl62391, isl62392, isl62391c, isl62392c (28 ld 4x4 tqfn) top view ordering information part number (note) part marking temp range (c) package (pb-free) pkg. dwg. # isl62391hrtz* 623 91hrtz -10 to +100 28 ld 4x4 tqfn l28.4x4 isl62392hrtz* 623 92hrtz -10 to +100 28 ld 4x4 tqfn l28.4x4 ISL62391CHRTZ* 62391c hrtz -10 to +100 28 ld 4x4 tqfn l28.4x4 isl62392chrtz* 62392c hrtz -10 to +100 28 ld 4x4 tqfn l28.4x4 isl62391irtz* 623 91irtz -40 to +100 28 ld 4x4 tqfn l28.4x4 isl62392irtz* 623 92irtz -40 to +100 28 ld 4x4 tqfn l28.4x4 isl62391cirtz* 62391c irtz -40 to +100 28 ld 4x4 tqfn l28.4x4 isl62392cirtz* 62392c irtz -40 to +100 28 ld 4x4 tqfn l28.4x4 *add ?-t*? suffix for tape and reel. pleas e refer to tb347 for details on reel specifications. note: these intersil pb-free plasti c packaged products employ special pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 terminat ion finish, which is rohs compliant and compatible with both snpb and pb-free soldering operations). intersil pb-free products are msl classified at pb-free peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jedec j std-020. fb2 vout2 isen2 ocset2 en2 phase2 ugate2 vout1 isen1 ocset1 en1 phase1 ugate1 boot1 pgood fset2 fccm vcc ldo3en fset1 fb1 boot2 lgate2 pgnd pvcc vin ldo3 lgate1 1 2 3 4 5 6 7 21 20 19 18 17 16 15 28 27 26 25 24 23 22 8 9 10 11 12 13 14 center pad: gnd data sheet april 7, 2011
2 fn6666.5 april 7, 2011 absolute m aximum ratings vin to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +28v vcc, pgood, pvcc to gnd . . . . . . . . . . . . . . . . . . -0.3v to +7.0v en 1, 2 , ldo3en . . . . . . . . . . . . . . . . . . . -0.3v to gnd, vcc +0.3v vout 1,2 , fb 1,2 , fset 1,2 . . . . . . . . . . . . -0.3v to gnd, vcc +0.3v phase 1,2 to gnd . . . . . . . . . . . . . . . . . . . . . . . (dc) -0.3v to +28v (<100ns pulse width, 10j) . . . . . . . . . . . . . . . . . . . . . . . . . -5.0v boot 1,2 to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +33v boot 1,2 to phase 1,2 . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +7v ugate 1,2 . . . . . . . . . . . . (dc) -0.3v to phase 1,2 , boot 1,2 +0.3v (<200ns pulse width, 20j) . . . . . . . . . . . . . . . . . . . . . . . . -4.0v lgate 1,2 . . . . . . . . . . . . . . . . . . . (dc) -0.3v to gnd, pvcc +0.3v (<100ns pulse width, 4j) . . . . . . . . . . . . . . . . . . . . . . . . . . -2.0v ldo3 current (internal regulator) continuous . . . . . . . . . +100ma thermal information thermal resistance (typical, notes 1, 2) ja (c/w) jc (c/w) tqfn package . . . . . . . . . . . . . . . . . . 37 3.5 junction temperature range. . . . . . . . . . . . . . . . . .-55 c to +150c operating temperature range isl62391irtz). . . . . . . . . . . . . . . . . . . . . . . . . . .-40 c to +100c isl62392irtz). . . . . . . . . . . . . . . . . . . . . . . . . . .-40 c to +100c operating temperature range isl62391hrtz) . . . . . . . . . . . . . . . . . . . . . . . . . .-10 c to +100c isl62392hrtz) . . . . . . . . . . . . . . . . . . . . . . . . . .-10 c to +100c storage temperature . . . . . . . . . . . . . . . . . . . . . . . .-65 c to +150c pb-free reflow profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/pb-freereflow.asp recommended operating conditions ambient temperature range isl62391irtz). . . . . . . . . . . . . . . . . . . . . . . . . . .-40c to +100c isl62392irtz). . . . . . . . . . . . . . . . . . . . . . . . . . .-40c to +100c ambient temperature range isl62391hrtz) . . . . . . . . . . . . . . . . . . . . . . . . . .-10c to +100c isl62392hrtz) . . . . . . . . . . . . . . . . . . . . . . . . . .-10c to +100c supply voltage (vin to gnd) . . . . . . . . . . . . . . . . . . . . 5.5v to 25v caution: do not operate at or near the maximum ratings listed fo r extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 1. ja is measured in free air with the component mounted on a high ef fective thermal conductivity te st board with ?direct attach? fe atures. see tech brief tb379. 2. for jc , the ?case temp? location is the center of the exposed metal pad on the package underside. electrical specifications vin = 12v, en = vcc, t a = -40c to +100c , unless otherwise noted. typical values are at t a = +25c. boldface limits apply over the operating temperature range. parameter conditions min (note 4) typ max (note 4) units linear regulator vin power-on reset rising threshold 5.3 5.4 5.5 v hysteresis 20 80 150 mv vin shutdown supply current en1 = en2 = ldo3en = 0 6 15 a vin standby supply current en1 = en2 = 0, ldo3en = 1 150 250 a ldo3 output voltage i_ldo3 = 100ma 3.25 3.3 3.35 v i_ldo3 = 0ma 3.25 3.3 3.35 v ldo3 short-circuit current ldo3 = gnd 180 ma ldo3en input voltage rising edge 1.1 2.5 v falling edge 0.94 1.06 v ldo3en input leakage current ldo3en = 0 or vcc -1 1 a ldo3 discharge on-resistance ldo3en = 0 36 60 pvcc por threshold 4.2 v smps2 to pvcc switchover threshold 4.63 4.8 4.93 v smps2 to pvcc switchover resistance vout2 to pvcc, vout2 = 5v 2.5 3.2 main smps controllers vcc input bias current en1 = en2 = 1, fb1 = fb2 = 0.65v 2 ma vcc start-up voltage en1 = en2 = ldo3en = gnd 3.45 3.6 3.75 v isl62391, isl62392, isl62391c, isl62392c
3 fn6666.5 april 7, 2011 vcc por threshold rising edge 4.33 4.50 4.55 v rising edge (isl62391hrtz, isl62392hrtz, t a = -10c to +100c) 4.35 4.50 4.55 v falling edge 4.08 4.20 4.30 v falling edge (isl62391hrtz, isl62392hrtz, t a = -10c to +100c) 4.10 4.20 4.30 v reference voltage 0.6 v regulation accuracy vout regulated to 0.6v -1 1 % fb input bias current fb = 0.6v -12 30 na fb = 0.6v (isl62391hrtz, isl62392hrtz, t a = -10c to +100c) -10 30 na frequency range 200 600 khz frequency set accuracy f sw = 300khz (note 3) -12 12 % vout voltage adjust range vin 6v for vout = 5.5v 0.6 5.5 v vout soft-discharge resistance 14 50 pgood pull-down impedance 32 50 pgood leakage current pgood = vcc 0 1 a maximum pgood sink current 5ma pgood soft-start delay (from first en = 1 to pgood = 1) en1 = en2 = 1 2.20 2.75 3.70 ms en1 = 1, en2 = floating or en1 = floating, en2 =1 4.50 5.60 7.60 ms en1 = 1, en2 = floating or en1 = floating, en2 =1 (isl62391hrtz, isl62392hrtz, t a = -10c to +100c) 4.50 5.60 7.50 ms ugate pull-up on-resistance 200ma source current 1.0 1.5 ugate source current ugate-phase = 2.5v 2.0 a ugate pull-down on-resistance 250ma source current 1.0 1.5 ugate sink current ugate-phase = 2.5v 2.0 a lgate pull-up on-resistance 250ma source current 1.0 1.5 lgate source current lgate-pgnd = 2.5v 2.0 a lgate pull-down on-resistance 250ma source current 0.5 0.9 lgate sink current lgate-pgnd = 2.5v 4.0 a ugate to lgate deadtime ug falling to lg rising, no load 21 ns lgate to ugate deadtime lg falling to ug rising, no load 21 ns bootstrap diode forward voltage 2ma forward diode current 0.58 v bootstrap diode reverse leakage current v r = 25v 0.2 1 a fccm input voltage low level (dcm enabled) 0.8 v float level (audio filter enabled) 1.9 2.1 v high level (forced ccm) 2.4 v fccm input leakage current fccm = gnd or vcc -2 2 a audio filter switching frequency fccm floating 28 khz en input voltage low level (clear fault level/smps off) 0.8 v float level (delayed start) 1.9 2.1 v high level (smps on) 2.4 v electrical specifications vin = 12v, en = vcc, t a = -40c to +100c , unless otherwise noted. typical values are at t a = +25c. boldface limits apply over the operating temperature range. (continued) parameter conditions min (note 4) typ max (note 4) units isl62391, isl62392, isl62391c, isl62392c
4 fn6666.5 april 7, 2011 en input leakage current en = gnd or vcc -3.5 3.5 a isen input impedance en = vcc 600 k isen input leakage current en = gnd 0.1 a ocset input impedance en = vcc 600 k ocset input leakage current en = gnd 0.1 a ocset current source en = vcc 8.7 10.0 10.5 a en = vcc (isl62391hrtz, isl62392hrtz, t a = -10c to +100c) 9 10.0 10.5 a ocp (ocset-isen) threshold -1.75 0.0 1.75 mv uvp threshold falling edge, referenced to fb 80.9 84 87 % falling edge, referenced to fb (isl62391hrtz, isl62392hrtz, t a = -10c to +100c) 81 84 87 % ovp threshold rising edge, referenced to fb 113 116 120 % falling edge, referenced to fb 99.5 103 106 % otp threshold rising edge 150 c falling edge 135 notes: 3. f sw accuracy reflects ic tolerance only; it does not include frequency variation due to v in , v out , l out , esr cout , or other application specific parameters. 4. compliance to datasheet limits is as sured by one or more methods: producti on test, characterization and/or design. electrical specifications vin = 12v, en = vcc, t a = -40c to +100c , unless otherwise noted. typical values are at t a = +25c. boldface limits apply over the operating temperature range. (continued) parameter conditions min (note 4) typ max (note 4) units isl62391, isl62392, isl62391c, isl62392c
5 fn6666.5 april 7, 2011 functional pin description pin name function 1 pgood open-drain power-good status outputs. connect to vcc through a 100k resistor. output will be high when all outputs are within regulation with no faults detected. 2 fset2 frequency control input for smps2. connect a resistor to ground to program the switching frequency. the pin output is a pulsed current and requires a decoupl ing capacitor to average the signal. 3 fccm logic input to control efficiency mode. logic high forc es continuous conduction mode (c cm). logic low allows full discontinuous conduction mode (dcm). float this pin for ultrasonic dcm operation. 4 vcc analog power supply input for reference voltages and currents . bypass to ground with a 1f ceramic capacitor near the ic. 5 ldo3en logic input for enabling and disabling the ldo3 linear regulator. positive logic input. 6 fset1 frequency control input for smps1. connect a resistor to ground to program the switching frequency. the pin output is a pulsed current and requires a decoupl ing capacitor to average the signal. 7 fb1 smps1 feedback input used for output voltage programming and regulation. 8 vout1 smps1 output voltage sense input. used for soft-discharge. 9 isen1 smps1 dcr current sense input. used for overcurrent protection and r 3 regulation. 10 ocset1 input from dcr current-sensing network used to pr ogram the overcurrent shutdown threshold for smps1. 11 en1 logic input to enable and disable smps1. a logic high will immediately enable smps1. floating this pin will enable smps1 only after smps2 has been enabled and achiev ed regulation. a logic low disables smps1. 12 phase1 smps1 switching node for high-side gate drive return and syn thetic ripple modulation. connect to the switching nmos source, the synchronous nmos drain, and the output inductor for smps1. 13 ugate1 high-side nmos gate drive output for smps1. connect to the gate of the smps1 switching fet. 14 boot1 smps1 bootstrap input for the switching nmos gate driver s. connect to smps1 phase with a ceramic capacitor of 0.22f. 15 lgate1 low-side nmos gate drive output for smps1. connect to the gate of the smps1 synchronous fet. 16 ldo3 3.3v linear regulator output, capable of providing 100ma continuous current. bypass to ground with a 4.7f ceramic capaci tor. 17 vin feed-forward input for line voltage transient com pensation. connect to the power train input voltage. 18 pvcc 5v power source for smps gate drive current. bypass to ground with a 4.7f ceramic capacitor. 19 pgnd power ground for smps1 and smps2. this provides a return path for synchronous fet switching currents. 20 lgate2 low-side nmos gate drive output for smps2. connect to the gate of the smps2 synchronous fet. 21 boot2 smps2 bootstrap input for the switching nmos gate driver s. connect to smps2 phase with a ceramic capacitor of 0.22f. 22 ugate2 high-side nmos gate drive output for smps2. connect to the gate of the smps2 switching fet. 23 phase2 smps2 switching node for high-side gate drive return and syn thetic ripple modulation. connect to the switching nmos source, the synchronous nmos drain, and the output inductor for smps2. 24 en2 logic input to enable and disable smps2. a logic high will immediately enable smps2. floating this pin will enable smps2 only after smps1 has been enabled and achiev ed regulation. a logic low disables smps2. 25 ocset2 input from dcr current-sensing network used to pr ogram the overcurrent shutdown threshold for smps2. 26 isen2 smps2 dcr current sense inpu t. used for overcurrent protection and r 3 regulation. 27 vout2 smps2 output voltage sense input. used for soft-discharge and switchover for pvcc 5v ldo. 28 fb2 smps2 feedback input used for output voltage programming and regulation. bottom pad gnd analog ground for analog and logic signals. isl62391, isl62392, isl62391c, isl62392c
6 fn6666.5 april 7, 2011 typical application circuits the typical application circuits generate the 5v/8a and 3.3v/8a (s ystem regulator), or 1.05v/15a and 1.5v/15a (chip set) suppli es in a notebook computer. the input supply (vbat) range is 5.5v to 25v. figure 1. typical system regulator application circuit with inductor dcr current sense figure 2. typical system regulator application circuit with resistor sense vbat vin phase1 ugate1 lgate1 ocset1 isen1 vout1 fb1 phase2 ugate2 lgate2 ocset2 isen2 vout2 fb2 3.3v 5v ldo3 pvcc vcc pvcc pgood pgnd pad en1 en2 fset1 fset2 boot1 boot2 fccm ldo3en 0.22f 0.22f irf7821 irf7821 irf7832 irf7832 4.7h 4.7h 9.09k 68.1k 750 1200pf 14k 14k 0.022f 100k 0.01f 0.01f 19.6k 24.3k 1f 4.7f 10k 45.3k 1f 330f 330f 1200pf 750 14k 14k 0.022f 4x10f isl62391, isl62392 isl62391c, isl62392c vbat vin phase1 ugate1 lgate1 ocset1 is e n 1 vout1 fb1 phase2 ugate2 lgate2 ocset2 isen2 vout2 fb2 3.3v 5v 3.3v ldo3 pvcc vcc pvcc pgood pgnd gnd en1 en2 fset1 fset2 boot1 boot2 fccm ldo3en 0.22f 0.22f irf7821 irf7821 irf7832 irf7832 4.7h 4.7h 4x10f isl62391, isl62392 0.01f 0.01f 24.3k 19.6k 1f 1f 4.7f 9.09k 68.1k 1200pf 1200pf 750 750 100k 45.3k 10k 330f 330f 0.001 0.001 1k 1k 1k 1k isl62391c, isl62392c isl62391, isl62392, isl62391c, isl62392c
7 fn6666.5 april 7, 2011 figure 3. typical chip set application circuit with inductor dcr current sense figure 4. typical chip set application circuit with resistor sense typical application circuits (continued) vbat vin phase1 ugate1 lgate1 ocset1 is e n 1 vout1 fb1 phase2 ugate2 lgate2 ocset2 is e n 2 vout2 fb2 1.05v 1.5v ldo3 pvcc vcc pvcc pgood pgnd pad en1 en2 fset1 fset2 boot1 boot2 fccm ldo3en 0.22f 0.22f irf7821 irf7821 irf7832 irf7832 2.2h 2.2h 24.3k 36.5k 590 1800pf 14k 14k 0.022f 100k 0.01f 0.01f 14k 17.4k 1f 4.7f 48.7k 36.5k 1f 2x330f 2x330f 1800pf 590 14k 14k 0.022f 4x10f isl62391, isl62392 2x 2x 2x 2x isl62391c, isl62392c vbat vin phase1 ugate1 lgate1 ocset1 is e n 1 vout1 fb1 phase2 ugate2 lgate2 ocset2 isen2 vout2 fb2 1.05v 1.5v 3.3v ldo3 pvcc vcc pvcc pgood pgnd gnd en1 en2 fset1 fset2 boot1 boot2 fccm ldo3en 0.22f 0.22f irf7821 irf7832 irf7832 2.2h 2.2h 4x10f isl62391, isl62392 0.01f 0.01f 17.4k 14k 1f 1f 4.7f 48.7k 36.5k 1800pf 1800pf 590 590 100k 36.5k 24.3k 2x330f 2x330f 0.001 0.001 1k 1k 1k 1k irf7821 2x 2x 2x 2x isl62391c, isl62392c isl62391, isl62392, isl62391c, isl62392c
8 fn6666.5 april 7, 2011 block diagram v ref 0.6v r 3 modulator fset1/2 fb1/2 ugate driver lgate driver pwm vin vout1/2 boot1/2 soft discharge pvcc pgnd lgate1/2 phase1/2 ugate1/2 fccm 5v ldo start-up and shutdown logic en1 ldo3en en2 ocset1/2 isen1/2 10a ocp protection logic ovp/uvp/ocp/otp pgood v ref + 16% v ref - 16% ovp uvp fb1/2 thermal monitor 3.3v ldo pvcc ldo3 soft discharge 4.8v vout2* vcc bias and reference t-pad *in addition to being used for regulation, vout2 will also provide power for pvcc when it is programmed to 5v. isl62391, isl62392, isl62391c, isl62392c
9 fn6666.5 april 7, 2011 typical performance curves figure 5. channel 1 efficiency at v o =3.3v, dem operation. high-side 1xirf7821, r ds(on) =9.1m ; low-side 1xirf7832, r ds(on) =4m ; l = 4.7h, dcr = 14.3m ; ccm f sw = 270khz figure 6. channel 2 efficiency at v o =5v, dem operation. high-side 1xirf7821, r ds(on) =9.1m ; low-side 1xirf7832, r ds(on) =4m ; l = 4.7h, dcr = 14.3m ; ccm f sw = 330khz figure 7. power-on, v in = 12v, load = 5a, v o =3.3v figure 8. power-off, v in = 12v, i o =5a, v o =3.3v figure 9. enable control, en1 = high, v in = 12v, v o = 3.3v, i o =5a figure 10. enable control, en1 = low, v in = 12v, v o = 3.3v, i o =5a 50 55 60 65 70 75 80 85 90 95 100 0.10 1.00 10.00 i out (a) efficiency (%) v in = 7v v in = 12v v in = 19v 50 55 60 65 70 75 80 85 90 95 100 0.01 0.10 1.00 10.00 i out (a) efficiency (%) v in = 7v v in = 12v v in = 19v v o1 fb1 pgood phase1 v o1 fb1 pgood phase1 v o1 fb1 pgood en1 v o1 fb1 pgood en1 isl62391, isl62392, isl62391c, isl62392c
10 fn6666.5 april 7, 2011 figure 11. ccm steady-state operation, v in = 12v, v o1 = 3.3v, i o1 =5a, v o2 =5v, i o2 =5a figure 12. dcm steady-state operation, v in =12v, v o1 = 3.3v, i o1 = 0. 2a, v o2 =5v, i o2 = 0.2a figure 13. audio filter operation, v in = 12v, v o1 = 3.3v, v o2 = 5v, no load figure 14. transient response, v in = 12v, v o =3.3v, i o = 0.1a/8.1a @ 2.5a/s figure 15. load insertion response, v in =12v, v o = 3.3v, i o = 0.1a/8.1a @ 2.5a/s figure 16. load release response, v in =12v, v o = 3.3v, i o = 0.1a/8.1a @ 2.5a/s typical performance curves (continued) phase2 v o2 phase1 v o1 v o1 phase1 v o2 phase2 v o1 phase1 v o2 phase2 i o1 v o1 phase1 v o1 phase1 i o1 v o1 phase1 i o1 isl62391, isl62392, isl62391c, isl62392c
11 fn6666.5 april 7, 2011 figure 17. delayed start, v in = 12v, v o1 =3.3v, v o2 =5v, en2 = float, no load figure 18. delayed start, v in =12v, v o1 =3.3v, v o2 =5v, en1 = float, no load figure 19. delayed start, v in = 12v, v o1 =3.3v, v o2 =5v, en1 = 1, en2 = float, no load figure 20. overcurrent protection, v in =12v, v o =3.3v figure 21. crowbar o vervoltage protection, v in =12v, v o = 3.3v, no load figure 22. tri-state overvoltage protection, v in = 12v, v o = 3.3v, no load typical performance curves (continued) en1 v o1 v o2 v o2 en2 v o1 v o1 pgood v o2 i o1 pgood v o1 pgood lgate1 v o1 ugate1-phase1 pgood lgate1 v o1 ugate1-phase1 isl62391, isl62392, isl62391c, isl62392c
12 fn6666.5 april 7, 2011 theory of operation three output controller the isl62391, isl62392, isl62391c and isl62392c generate three regulated output voltages. two are produced with switch-mode power supplies (smps), and the third by a low dropout linear regulator (ldo). an additional 5v ldo (pvcc) is used to power the chip during operation, allowing the isl62391, isl62392, isl62391c and isl62392c to regulate all outputs from a single power source (vin) with no need for a separate quiescent supply. this makes the isl62391, isl62392, isl62391c and isl62392c an ideal choice as system regulator for notebook pcs. because the two smps channels are identic al and almost entirely independent, all conclusions drawn apply to both channels unless otherwise noted. modulator and switching frequency the isl62391, isl62392, isl62391c and isl62392c modulator feature intersil?s r 3 technology, a hybrid of fixed frequency pwm and variable freq uency hysteretic control. intersil?s r 3 technology can simultaneously affect the pwm switching frequency and pwm du ty cycle in response to input voltage and output load transients. the r 3 modulator synthesizes an ac signal, v r , which is an analog representation of the output inductor ripple current. the duty-cycle of v r is the result of charge and discharge current through a ripple capacitor, c r . the current through c r is provided by a transco nductance amplifier that measures the vin and vo pin voltages. the positive slope of v r can be written as equation 1: the negative slope of v r can be written as equation 2: where g m is the gain of the transconductance amplifier. a window voltage v w is referenced with respect to the error amplifier output voltage v comp , creating an envelope into which the ripple voltage v r is compared. the amplitude of v w is set by a resistor, r w , connected across the fset and gnd pins. the v r, v comp, and v w signals feed into a window comparator in which v comp is the lower threshold voltage and v w is the higher threshold voltage. figure 23 shows pwm pulses being generated as v r traverses the v w and v comp thresholds. the pwm switching frequency is proportional to the slew ra tes of the positive and negative slopes of v r; it is inversely proportional to the voltage between v w and v comp. equation 3 illustrates how to calculate the window size based on output voltage and frequency set resistor. the frequency can be expressed in equation 4: inverting equation 4 allows easy selection of r w for a desired f sw : for equations 3 through 5: g m = 1.66s k = 1.7 x 10 -10 (20%) d = v out /v in power-on reset the isl62391, isl62392, isl62391c and isl62392c are disabled until the voltage at the vin pin has increased above the rising power-on reset (por) threshold. conversely, the controller will be disabled when the voltage at the vin pin decreases below the falling por threshold. in addition to vin por, the pvcc pi n is also monitored. if its voltage falls below 4.2v, the smps outputs will be shut down. this ensures that there is sufficient boot voltage to enhance the upper mosfet. en, soft-start and pgood the isl62391, isl62392, isl62391c and isl62392c use a digital soft-start circuit to ramp the output voltage of each smps to the programmed regulation setpoint at a predictable slew rate. the slew rate of the soft-start sequence has been selected to limit the in-rush current through the output capacitors as they charge to the desired regulation voltage. when the en pins are pulled above their rising thresholds, the pgood soft-start delay, t ss , starts and the output voltage begins to rise. the fb pin ramps to 0.6v in approximately 1.5ms and t he pgood pin goes to high impedance approximately 1.25ms after the fb pin voltage reaches 0.6v. v rpos g m v in v out ? () ? = (eq. 1) v rneg g m v out ? = (eq. 2) figure 23. modulator waveforms during load transient pwm ripple capacitor voltage c r error amplifier window voltage v w (wrt v comp ) voltage v comp v w g m v out 1d ? () r w ?? ? = (eq. 3) f sw 1 kr w ? ----------------- - = (eq. 4) r w 1 kf sw ? -------------------- - = (eq. 5) isl62391, isl62392, isl62391c, isl62392c
13 fn6666.5 april 7, 2011 the pgood pin indicates when the converter is capable of supplying regulated voltage. it is an undefined impedance if v in is not above the rising por threshold or below the por falling threshold. when a fault is detected, the isl62391, isl62392, isl62391c and isl62392c will turn on the open- drain nmos, which will pull pgood low with a nominal impedance of 32 . this will flag the system that one of the output voltages is out of regulation. separate enable pins allow for full soft-start sequencing. because low shutdown quiescent current is necessary to prolong battery life in notebook applications, the pvcc 5v ldo is held off until any of the three enable signals (en1, en2 or ldo3en) are pulled high. soft-start of all outputs will only start until after pvcc is above the 4.2v por threshold. in addition to user-programmable sequencing, the isl62391, isl62392, isl62391c and isl62392c include a pre- programmed sequential smps soft-start feature. table 1 shows the smps enable truth table. vcc the vcc nominal operation voltage is 5v. if en1, en2 and ldo3en are all logic low, the vcc start-up voltage is 3.6v when vin is applied on isl62391, isl62392, isl62391c and isl62392c. pvcc is held off until any of the three enable signals (en1, en2 or ldo3en) is pulled high. when pvcc is above the 4.2v vcc por threshold, vcc will switchover to pvcc internally. after vin is applied, the vcc start-up 3.6v voltage can be used as the logic high signal of any of en1, en2 and ldo3en to enable pvcc if there is no ot her power supply on the board. mosfet gate-drive outputs lgate and ugate the isl62391, isl62392, isl62391c and isl62392c have internal gate-drivers for the high-side and low-side n- channel mosfets. the low-side gate-drivers are optimized for low duty-cycle applications where the low-side mosfet conduction losses are dominant, requiring a low r ds(on) mosfet. the lgate pull-down resistance is small in order to clamp the gate of the mosfet below the v gs(th) at turn- off. the current transient through the gate at turn-off can be considerable because the gate charge of a low r ds(on) mosfet can be large. adaptiv e shoot-through protection prevents a gate-driver output fr om turning on until the opposite gate-driver output has fallen below approximately 1v. the dead-time shown in figure 25 is extended by the additional period that the falling gate voltage stays above the 1v threshold. the typical dead-time is 21ns. the high-side gate- driver output voltage is me asured across the ugate and phase pins while the low-side gat e-driver output voltage is measured across the lgate and pgnd pins. the power for the lgate gate-driver is sourced directly from the pvcc pin. the power for the ugate gate-driver is sourced from a ?boot? capacitor connected across the boot and phase pins. the boot capacitor is charged from the 5v pvcc supply through a ?boot diode? each time the low-side mosfet turns on, pulling the phase pin low. the isl62391, isl62392, isl62391c and isl62392c have integrated boot diodes connected from the pvcc pins to boot pins. diode emulation fccm is a logic input that controls the power state of the isl62391, isl62392, isl62391c and isl62392c. if forced high, the isl62391, isl62392, isl62391c and isl62392c will operate in forced cont inuous-conduction-mode (ccm) table 1. smps enable sequence logic en1 en2 start-up sequence 0 0 all smps outputs off 0 float all smps outputs off 0 1 smps1 off, smps2 on float 0 all smps outputs off float float all smps outputs off float 1 smps1 enables after smps2 is in regulation 1 0 smps1 on, smps2 off 1 float smps2 enables after smps1 is in regulation 1 1 all smps outputs on simultaneously figure 24. soft-start sequence for one smps vcc and pvcc vo en pgood fb 1.5ms 2.75ms t softstart pgood delay figure 25. lgate and ugate dead-time 50% 50% t lgfugr t ugflgr ugate lgate isl62391, isl62392, isl62391c, isl62392c
14 fn6666.5 april 7, 2011 over the entire load range. this will produce the best transient response to all load conditions, but will have increased light-load power loss. if fccm is forced low, the isl62391, isl62392, isl62391c and isl62392c will automatically operate in diode emulation mode (dem) at light load to optimize efficiency in the ent ire load range. the transition is automatically achieved by det ecting the load current and turning off lgate when the inductor current reaches 0a. positive-going inductor current flows from either the source of the high-side mosfet, or the drain of the low-side mosfet. negative-going inductor current flows into the drain of the low-side mosfet. when the low-side mosfet conducts positive inductor current, the phase voltage will be negative with respect to the gnd and pgnd pins. conversely, when the low-side mosfet conducts negative inductor current, the phase voltage will be positive with respect to the gnd and pgnd pins. the isl62391, isl62392, isl62391c and isl62392c monitor the phase voltage when the low-side mosfet is conducting inductor current to determine its direction. when the output load current is greater than or equal to ? the inductor ripple current, the inductor current is always positive, and the converter is always in ccm. the isl62391, isl62392, isl62391c and isl62392c minimize the conduction loss in this condition by forcing the low-side mosfet to operate as a synchronous rectifier. when the output load current is less than ? the inductor ripple current, negative inductor current occurs. sinking negative inductor through the low-side mosfet lowers efficiency through unnecessary conduction losses. the isl62391, isl62392, isl62391c and isl62392c automatically enter dem afte r the phase pin has detected positive voltage and lgate was allowed to go high for 8 consecutive pwm switching cycles. the isl62391, isl62392, isl62391c and isl62392c will turn off the low- side mosfet once the phase voltage turns positive, indicating negative inductor current. the isl62391, isl62392, isl62391c and isl62392c will return to ccm on the following cycle after the phase pin detects negative voltage, indicating that the body diode of the low-side mosfet is conducting positive inductor current. efficiency can be further improved with a reduction of unnecessary switching losse s by reducing the pwm frequency. it is characteristic of the r 3 architecture for the pwm frequency to decrease while in diode emulation. the extent of the frequency redu ction is proportional to the reduction of load current. upon entering dem, the pwm frequency makes an initial step -reduction because of a 33% step-increase of the window voltage v w . because the switching frequency in dem is a function of load current, very light load conditions can produce frequencies well into the audio band. this can be problematic if audible noise is coupled into audio amplifier circuits. to prevent this from occurring, the isl62391, isl62392, isl62391c and isl62392c allow the user to float the fccm input. this will allow dem at light loads, but will prevent the switching frequency from going below ~28khz to prevent noise injection to the audio band. a timer is reset each pwm pulse. if the timer exceeds 30s, lgate is turned on, causing the ramp voltage to reduce until another ugate is commanded by the voltage loop. overcurrent protection the overcurrent protection (ocp) setpoint is programmed with resistor, r ocset , that is connected across the ocset and phase pins. figure 26 shows the overcurrent-set circuit for smps1. the inductor consists of inductance l and the dc resistance (dcr). the inductor dc current i l creates a voltage drop across dcr, which is given by equation 6: the isl62391, isl62392, isl62391c and isl62392c sink a 10a current into the ocset1 pin, creating a dc voltage drop across the resistor r ocset , which is given by equation 7: resistor r o is connected between the isen1 pin and the actual output voltage of the converter. during normal operation, the isen1 pin is a high impedance path, therefore there is no voltage drop across r o . the dc voltage difference between the ocset1 pin and the isen1 pin can be established using equation 8: the isl62391, isl62392, isl62391c and isl62392c monitor the ocset1 pin and the isen1 pin voltages. once the ocset1 pin voltage is higher than the isen1 pin voltage for more than 10s, the isl62391, isl62392, isl62391c and isl62392c declare an ocp fault. the value of r ocset is then written as equation 9: figure 26. overcurrent-set circuit phase1 c o l v o r ocset c sen ocset1 isen1 r o isl62391, dcr i l 10a + _ v dcr + _ v rocset isl62392 v dcr i l dcr ? = (eq. 6) v rocset 10 ar ocset ? = (eq. 7) v ocset1 v ? isen1 i l dcr ? 10 ar ocset ? ? = (eq. 8) (eq. 9) r ocset i oc dcr ? 10 a --------------------------- = isl62391, isl62392, isl62391c, isl62392c
15 fn6666.5 april 7, 2011 where: -r ocset ( ) is the resistor used to program the overcurrent setpoint -i oc is the output current threshold that will activate the ocp circuit - dcr is the inductor dc resistance for example, if i oc is 20a and dcr is 4.5m , the choice of r ocset is r ocset = 20a x 4.5m /10a = 9k . resistor r ocset and capacitor c sen form an r-c network to sense the inductor current. to sense the inductor current correctly, not only in dc operation but also during dynamic operation, the r-c network time constant r ocset -c sen needs to match the inductor ti me constant l/dcr. the value of c sen is then written as equation 10: for example, if l is 1.5h, dcr is 4.5m , and r ocset is 9k , the choice of c sen = 1.5h/(9k x 4.5m ) = 0.037f . upon converter start-up, the c sen capacitor bias is 0v. to prevent false ocp during this time, a 10a current source flows out of the isen1 pin, generating a voltage drop on the r o resistor, which should be chosen to have the same resistance as r ocset . when the pgood pin goes high, the isen1 pin current source will be removed. when an ocp fault is declared, the pgood pin will pull-down to 32 and latch-off the converter. the fault will remain latched until the en pin has been pulled below the falling en threshold voltage, or until v in has decayed below the falling por threshold. when using a discrete current sense resistor, inductor time-constant matching is not required. equation 7 remains unchanged, but equation 8 is modified in equation 11: furthermore, equation 9 is changed in equation 12: where r sense is the series power resistor for sensing inductor current. for example, with an r sense = 1m and an ocp target of 10a, r ocset = 1k . overvoltage protection the ovp fault detection circuit triggers after the fb pin voltage is above the rising overvoltage threshold for more than 2s. the fb pin voltage is 0.6v in normal operation. the rising overvoltage threshold is typically 116% of that value, or 1.16*0.6v = 0.696v. for isl62391, isl62392, isl62391c and isl62392c, when an ovp fault is declared, the pgood pin will pull-down with 32 and latch-off the converter. the ovp fault will remain latched until the en pin has been pulled below the falling en threshold voltage, or until v in has decayed below the falling por threshold. during the latch condition, the isl62391 and isl62391c will tri-state the phase node by turning both ugate and lgate off until the latch is cleared. although latched, the isl62392 and isl62392c lgate gate- driver output will retain the ability to toggle the low-side mosfet on and off in response to the output voltage transversing the ovp rising and falling thresholds. the lgate gate-driver will turn on the low-side mosfet to discharge the output voltage, thus protecting the load from potentially damaging voltage levels. the lgate gate-driver will turn off the low-side mosfet once the fb pin voltage is lower than the falling overvoltage threshold for more than 2s. the falling overvoltage threshold is typically 106% of the reference voltage, or 1.06*0.6v = 0.636v. this soft-crowbar process repeats as long as the output voltage fault is present, allowing the isl62392 and isl62392c to protect against persistent overvoltage conditions. undervoltage protection the uvp fault detection circuit triggers after the fb pin voltage is below the undervoltage threshold for more than 2s. the undervoltage threshold is typically 86% of the reference voltage, or 0.86*0.6v = 0.516v. if a uvp fault is declared, the pgood pi n will pull-dow n with 32 and latch-off the converter. the fault will re main latched until the en pin has been pulled below the falling enable threshold, or if v in has decayed below the falling por threshold. programming the output voltage when the converter is in regul ation, there will be 0.6v between the fb and gnd pins. connect a two-resistor voltage divider across the out and gnd pins with the output node connected to the fb pin, as shown in figure 27. scale the voltage-divider network such that the fb pin is 0.6v with respect to the gnd pin when the converter is regulating at the desired out put voltage. the output voltage can be programmed from 0.6v to 5.5v. programming the output volta ge is written as equation 13: where: -v out is the desired output voltage of the converter - the voltage to which the converter regulates the fb pin is the v ref (0.6v) -r top is the voltage-programming resistor that connects from the fb pin to the converter output. in addition to setting the output voltage, this resistor is part of the loop compensation network -r bottom is the voltage-programming resistor that connects from the fb pin to the gnd pin choose r top first when compensati ng the control loop, and then calculate r bottom according to equation 14: (eq. 10) c sen l r ocset dcr ? ----------------------------------------- = v ocset1 v ? isen1 i l r sense ? 10 ar ocset ? ? = (eq. 11) r ocset i oc r sense ? 10 a ------------------------------------- = (eq. 12) v out v ref 1 r top r bottom ---------------------------- - + ?? ?? ?? ? = (eq. 13) isl62391, isl62392, isl62391c, isl62392c
16 fn6666.5 april 7, 2011 compensation design figure 27 shows the recommended type-ii compensation circuit. the fb pin is the inverting input of the error amplifier. the comp signal, the output of t he error amplifier, is inside the chip and unavailable to users. c int is a 100pf capacitor integrated inside the ic that connects across the fb pin and the comp signal. r top , r fb , c fb and c int form the type-ii compensator. the frequency domain transfer function is given by equation 15: the lc output filter has a double pole at its resonant frequency that causes rapid phase change. the r 3 modulator used in the isl62391, isl62392, isl62391c and isl62392c make the lc output filter rese mble a first order system in which the closed loop stability can be achieved with the recommended type-ii compensation network. intersil provides a pc-based tool (example page is shown later) that can be used to calculate compensation network component values and help simulate the loop frequency response. 3.3v linear regulator in addition to the two smps outputs, the isl62391, isl62392, isl62391c and isl62392c also provide a fixed 3.3v ldo output (ldo3) capable of sourcing 100ma continuous current. ldo3 draws its power from pvcc and can be independently enabled from both smps channels. ldo3 also has a current limit feature with a nominal level of 180ma. currents in excess of the limit will cause the ldo3 voltage to drop dramatically, limiting the power dissipation. thermal monitor and protection ldo3 and pvcc ldos can dissipate non-trivial power inside the isl62391, isl62392, isl62391c and isl62392c at high input-to-output voltage ratios and full load conditions. to protect the silicon, isl62391, isl6239 2, isl62391c and isl62392c continually monitor the die te mperature. if the temperature exceeds +150 c, all outputs will be turned off to sharply curtail power dissipation. the outputs will remain off until the junction temperature has fallen below +135 c. general application design guide this design guide is intended to provide a high-level explanation of the steps neces sary to design a single-phase power converter. it is assumed th at the reader is familiar with many of the basic skills and te chniques referenced in the following section. in addition to this guide, intersil provides complete reference designs that include schematics, bills of materials, and example board layouts. selecting the lc output filter the duty cycle of an ideal buck c onverter is a function of the input and the output voltage. this relationship is written as equation 16: the output inductor peak-to-peak ripple current is written as equation 17: a typical step-down dc/dc converter will have an i p-p of 20% to 40% of the maximum dc output load current. the value of i p-p is selected based upon se veral criteria, such as mosfet switching loss, inducto r core loss, and the resistive loss of the inductor winding. the dc copper loss of the inductor can be estimated by equation 18: where i load is the converter output dc current. the copper loss can be significant so attention has to be given to the dcr selection. another factor to consider when choosing the inductor is its sa turation characteristics at elevated temperature. a satu rated inductor could cause destruction of circuit components, as well as nuisance ocp faults. a dc/dc buck regulator must have output capacitance c o into which ripple current i p-p can flow. current i p-p develops a corresponding ripple voltage v p-p across c o, which is the sum of the voltage drop across the capacitor esr and of the voltage change stemming from charge moved in and out of the capacitor. these two voltages are written as equation 19: and equation 20: if the output of the converter has to support a load with high pulsating current, several capacitors will need to be paralleled to reduce the total esr until the required v p-p is achieved. r bottom v ref r ? top v out v ref ? ------------------------------------- = (eq. 14) (eq. 15) g comp s () 1sr top r fb + () c ? fb ? + sr top c int 1sr fb c ? fb ? + () ? ? ? ------------------------------------------------------------------------------------------- = isl62391, isl62392 r bottom ea + fb c int = 100pf - ref vo figure 27. compensation reference circuit r top r fb c fb comp d v o v in --------- = (eq. 16) (eq. 17) i pp v o 1d ? () ? f sw l ? ----------------------------- - = (eq. 18) p copper i load 2 dcr ? = v esr i p-p e ? sr = (eq. 19) v c i p-p 8c o f ? sw ? ----------------------------- = (eq. 20) isl62391, isl62392, isl62391c, isl62392c
17 fn6666.5 april 7, 2011 the inductance of the capacitor can cause a brief voltage dip if the load transient has an extremely high slew rate. low inductance capacitors should be considered in this scenario. a capacitor dissipates heat as a function of rms current and frequency. be sure that i p-p is shared by a sufficient quantity of paralleled capacitors so that they operate below the maximum rated rms current at f sw . take into account that the rated value of a capacitor can fade as much as 50% as the dc voltage across it increases. selection of the input capacitor the important parameters for the bulk input capacitance are the voltage rating and the rms current rating. for reliable operation, select bulk capacitors with voltage and current ratings above the maximum input voltage and capable of supplying the rms current requir ed by the switching circuit. their voltage rating should be at least 1.25x greater than the maximum input voltage, while a voltage rating of 1.5x is a preferred rating. figure 28 is a graph of the input rms ripple current (normalized relative to output load current) as a function of duty cycle and is adjusted for a converter efficiency of 80%. the ripple current calculation is written as equation 21: where: -i max is the maximum continuous i load of the converter - x is a multiplier (0 to 1) corresponding to the inductor peak-to-peak ripple amplitude expressed as a percentage of i max (0% to 100%) - d is the duty cycle that is adjusted to take into account the efficiency of the converter which is written as equation 22. in addition to the bulk capacitance, some low esl ceramic capacitance is recommended to decouple between the drain of the high-side mosfet and the source of the low-side mosfet. mosfet selection and considerations typically, a mosfet cannot tolerate even brief excursions beyond their maximum drain to source voltage rating. the mosfets used in the power stage of the converter should have a maximum v ds rating that exceeds the sum of the upper voltage tolerance of the input power source and the voltage spike that occurs when the mosfet switches off. there are several power mosfets readily available that are optimized for dc/dc converter applications. the preferred high-side mosfet emphasizes low gate charge so that the device spends the least amount of time dissipating power in the linear region. unlike the low-side mosfet, which has the drain-source voltage clamped by its body diode during turn off, the high-side mosfet turns off with a v ds of approximately v in -v out , plus the spike across it. the preferred low-side mosfet emphasizes low r ds(on) when fully saturated to minimize conduction loss. it should be noted that this is an optimal configuration of mosfet selection for low duty cycle ap plications (d < 50%). for higher output, low input voltage solutions, a more balanced mosfet selection for high- and low-side devices may be warranted. for the low-side (ls) mosfet, the power loss can be assumed to be conductive only and is written as equation 23: for the high-side (hs) mosfet, the conduction loss is written as equation 24: for the high-side mosfet, the switching loss is written as equation 25: (eq. 21) i in_rms normalized , dd 2 ? () d x 2 12 ------ ? ?? ?? + = d v o v in eff ? -------------------------- = (eq. 22) figure 28. normalized rms input current 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 0 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 0.55 0.60 normalized input rms ripple current duty cycle x = 1 x = 0.75 x = 0.50 x = 0.25 x = 0 (eq. 23) p con_ls i load 2 r ? ds on () _ls 1d ? () ? (eq. 24) p con_hs i load 2 r ? ds on () _hs d ? = (eq. 25) p sw_hs v in i valley t on f ? sw ? ? 2 ---------------------------------------------------------------- - v in i peak t off f ? sw ? ? 2 ------------------------------------------------------------- + = isl62391, isl62392, isl62391c, isl62392c
18 fn6666.5 april 7, 2011 where: -i valley is the difference of the dc component of the inductor current minus 1/2 of the inductor ripple current -i peak is the sum of the dc component of the inductor current plus 1/2 of the inductor ripple current -t on is the time required to drive the device into saturation -t off is the time required to drive the device into cut-off selecting the bootstrap capacitor the selection of the bootstrap capacitor is written as equation 26: where: -q g is the total gate charge required to turn on the high-side mosfet - v boot , is the maximum allowed voltage decay across the boot capacitor each time the high-side mosfet is switched on as an example, suppose the high-side mosfet has a total gate charge q g , of 25nc at v gs = 5v, and a v boot of 200mv. the calculated bootstrap capacitance is 0.125f; for a comfortable margin, select a capacitor that is double the calculated capacitance. in this example, 0.22f will suffice. use an x7r or x5r ceramic capacitor. layout considerations as a general rule, power should be on the bottom layer of the pcb and weak analog or logic signals are on the top layer of the pcb. the ground-pl ane layer should be adjacent to the top layer to provide shielding. the ground plane layer should have an island located under the ic, the compensation components, and the fset components. the island should be connected to the rest of the ground plane layer at one point. because there are two smps outputs and only one pgnd pin, the power train of both channels should be laid out symmetrically. the line of bilateral symmetry should be drawn through pins 4 and 18. this layout approach ensures that the controller does not favor one channel over another during critical switching decisions. figure 29 illustrates one example of how to achieve proper bilateral symmetry. signal ground and power ground the bottom of the isl62391, isl62392, isl62391c and isl62392c tqfn package is the signal ground (gnd) terminal for analog and logic signals of the ic. connect the gnd pad of the isl62391, isl62392, isl62391c and isl62392c to the island of ground plane under the top layer using several vias for a robust thermal and electrical conduction path. connect the input capacitors, the output capacitors, and the source of the lower mosfets to the power ground plane. pgnd (pin 19) this is the return path for the pull-down of the lgate low-side mosfet gate driver. ideally, pgnd should be connected to the source of the low-side mosfet with a low-resistance, low- inductance path. vin (pin 17) the vin pin should be connected close to the drain of the high-side mosfet, using a low resistance and low inductance path. vcc (pin 4) for best performance, place the decoupling capacitor very close to the vcc and gnd pins. pvcc (pin 18) for best performance, place the decoupling capacitor very close to the pvcc and respective pgnd pin, preferably on the same side of the pcb as the isl62391, isl62392, isl62391c and isl62392c ics. en (pins 11 and 24), and pgood (pin 1) these are logic signals that are referenced to the gnd pin. treat as a typical logic signal. ocset (pins 10 and 25) and isen (pins 9 and 26) for dcr current sensing, the current-sense network, consisting of r ocset and c sen , needs to be connected to the inductor pads for accurate measurement. connect c boot q g v boot ----------------------- - = (eq. 26) inductor vias to ground plane vin vout phase node gnd output capacitors low-side mosfets input capacitors schottky diode high-side mosfets figure 29. typical power component placement output capacitors schottky diode low-side mosfets input capacitors inductor high-side mosfets gnd vin vias to ground plane phase node line of symmetry pin 4 (vcc) pin 18 (pvcc) l2 ci co l1 ci co u2 l2 u1 l1 isl6239 pgnd plane phase planes vout planes vin plane figure 30. symmetric layout guide isl62391, isl62392, isl62391c, isl62392c
19 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com fn6666.5 april 7, 2011 r ocset to the phase-node side pad of the inductor, and connect c sen to the output side pad of the inductor. the isen resistor should also be co nnected to the output pad of the inductor with a separate trace. connect the ocset pin to the common node of node of r ocset and c sen . for resistive current sensing, connect r ocset from the ocset pin to the inductor side of the resistor pad. the isen resistor should be connected to the v out side of the resistor pad. in both current-sense configurations, the resistor and capacitor sensing elements, with the exclusion of the current sense power resistor, should be placed near the corresponding ic pin. the trace connections to the inductor or sensing resistor should be treated as kelvin connections. fb (pins 7 and 28), and vout (pins 8 and 27) the vout pin is used to generate the r 3 synthetic ramp voltage and for soft-discharge of the output voltage during shutdown events. this signal should be routed as close to the regulation point as possible. the input impedance of the fb pin is high, so place the voltage programming and loop compensation components close to the vout, fb, and gnd pins, keeping the high impedance trace short. fset (pins 2 and 6) this pin requires a quiet environment. the resistor r fset and capacitor c fset should be placed directly adjacent to this pin. keep fast moving nodes away from this pin. lgate (pins 15 and 20) the signal going through this trace is both high dv/dt and high di/dt, with high peak charging and discharging current. route this trace in parallel with the trace from the pgnd pin. these two traces should be short, wide, and away from other traces. there should be no other weak signal traces in proximity with these traces on any layer. boot (pins 14 and 21), ugate (pins 13 and 22), and phase (pins 12 and 23) the signals going through thes e traces are both high dv/dt and high di/dt, with high peak charging and discharging current. route the ugate and phase pins in parallel with short and wide traces. there should be no other weak signal traces in proximity with these traces on any layer. copper size for the phase node the parasitic capacitance and parasitic inductance of the phase node should be kept very low to minimize ringing. it is best to limit the size of the phase node copper in strict accordance with the current and thermal management of the application. an mlcc should be connected directly across the drain of the upper mosfet and the source of the lower mosfet to suppress the turn-off voltage spike. isl62391, isl62392, isl62391c, isl62392c
20 fn6666.5 april 7, 2011 isl62391, isl62392, isl62391c, isl62392c package outline drawing l28.4x4 28 lead thin quad flat no-lead plastic package rev 0, 9/06 typical recommended land pattern detail "x" top view bottom view notes: 1. controlling dimensions are in mm. dimensions in ( ) for reference only. 2. unless otherwise specified, tolerance : decimal 0.05 angular 2 3. dimensioning and tolerancing conform to amse y14.5m-1994 . 4. bottom side pin#1 id is diepad chamfer as shown. 5. tiebar shown (if present) is a non-functional feature. pin 1 index area 4 . 00 0 ~ 0 . 05 5 0 . 10 pin #1 index area chamfer 0 . 400 x 45? 2 . 50 2 . 50 3 . 20 a package boundary 4 . 00 0 . 40 0 . 20 ?0 . 0 0 . 40 0 . 20 ref 0 . 00 - 0 . 05 see detail x'' seating plane (28x 0 . 60) (0 . 40) (28x 0 . 20) (2 . 50) (2 . 50) (3 . 20) (3 . 20) 0 . 4 x 6 = 2.40 ref 3 . 20 0 . 4 x 6 = 2 . 40 ref max. 0 . 80 (0 . 40) b side view c c 0 . 20 ref 0 . 08 c 0 . 10 c 0 . 10 m c a b 2x 14 8 7 1 28 22 21 15

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